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HD404339 Series
Rev. 7.0 Sept. 1999 Description
The HD404339 Series is 4-bit HMCS400-Series microcomputer with large-capacity memory designed to increase program productivity. Each microcomputer has an A/D converter, input capture timer, and a 32kHz oscillator circuit for clock use all built in. They also come with high-voltage I/O pins that can directly drive a fluorescent display. The HD404339 Series includes six chips: the HD404339 with 16-kword ROM; the HD4043312 with 12kword ROM; the HD404338 with 8-kword ROM; the HD404336 with 6-kword ROM; the HD404334 with 4-kword ROM; the HD4074339 with 16-kword PROM. The HD4074339 is a PROM version ZTATTM microcomputer. Programs can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) ZTATTM: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
* 54 I/O pins One input-only pin 53 input/output pins: 30 pins are high-voltage pins (40 V, max.) * On-chip A/D converter (8-bit x 12-channel) * Three timers One event counter input One timer output One input capture timer * 8-bit clock-synchronous serial interface (1 channel) * Alarm output * Built-in oscillators Ceramic or crystal oscillator External clock drive is also possible Subclock: 32.768-kHz crystal oscillator
HD404339 Series
* Seven interrupt sources Two by external sources Three by timers One each by the A/D converter and serial interface * Four low-power dissipation modes Standby mode Stop mode Watch mode Subactive mode * Instruction cycle time: 1 s (fOSC = 4 MHz, 1/4 division ratio) 1/4, 1/8, 1/16, 1/32 system clock division ratio can be selected
Ordering Information
Type Mask ROM Product Name HD404334 Model Name HD404334S HD404334FS HD404336 HD404336S HD404336FS HD404338 HD404338S HD404338FS HD4043312 HD4043312S HD4043312FS HD404339 HD404339S HD404339FS ZTATTM HD4074339 HD4074339S HD4074339FS 16,384 16,384 12,288 8,912 6,144 ROM (words) 4,096 RAM (digit) 512 Package DP-64S FP-64B DP-64S FP-64B DP-64S FP-64B DP-64S FP-64B DP-64S FP-64B DP64S FP-64B
Recommended PROM Programmers and Socket Adapters
PROM Programmer Manufacture DATA I/O corp Model Name 121 B Socket Adapter Package DP-64S FP-64B AVAL corp PKW-1000 DP-64S FP-64B Hitachi Manufacture Hitachi Model Name HS4339ESS01H HS4339ESF01H HS4339ESS01H HS4339ESF01H
2
HD404339 Series
Pin Arrangement
R71 R70 R63 R62 R61 R60 RA1/Vdisp R23 R22 R21 R20 R13 R12 R60 R61 R62 R63 R70 R71 R72 R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND X1 X2 AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 R42/AN6 R43/AN7 R50/AN8 R51/AN9 R52/AN10 R53/AN11 AV CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RA1/Vdisp R23 R22 R21 R20 R13 R12 R11 R10 R93 R92 R91 R90 R83 R82 R81 R80 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4/STOPC D3/BUZZ D2/EVNB D1/INT1 D0/INT0 VCC
64 63 62 61 60 59 58 57 56 55 54 53 52 R72 R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND X1 X2 AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
FP-64B
R11 R10 R93 R92 R91 R90 R83 R82 R81 R80 D13 D12 D11 D10 D9 D8 D7 D6 D5
DP-64S
R42/AN6 R43/AN7 R50/AN8 R51/AN9 R52/AN10 R53/AN11 AVCC VCC D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC
20 21 22 23 24 25 26 27 28 29 30 31 32
3
HD404339 Series
Pin Description
Pin Number Item Power supply Symbol VCC GND Vdisp (shared with RA1) Test Reset Oscillator TEST RESET OSC 1 12 13 14 6 7 8 I I I DP-64S 33 16 64 FP-64B 27 10 58 I/O Function Applies power voltage Connected to ground Used as a high-voltage output power supply pin when selected by the mask option
Cannot be used in user applications. Connect this pin to GND. Resets the MCU Input/output pin for the internal oscillator. Connect these pins to the ceramic or crystal oscillator, or OSC1 to an external oscillator circuit.
OSC 2 X1 X2 Port D0-D 13
15 17 18 34-47
9 11 12 28-41
O I O I/O Input/output pins addressed individually by bits; D0-D 13 are all high-voltage I/O pins. Each pin can be individually configured as selected by the mask option. One-bit high-voltage input port pin Four-bit input/output pins consisting of standard voltage pins Used with a 32.768-kHz crystal oscillator for clock purposes
RA 1
64
58 1-5, 14-25, 59-64
I I/O
R0 0-R0 3, 1-11, R3 -R7 20-31
0 2
R1 0-R2 3, 48-63 R8 0-R9 3 Interrupt Stop clear INT0, INT1 34, 35 STOPC 38 8 9 10 11 36 37
42-57
I/O
Four-bit input/output pins consisting of high voltage pins Input pins for external interrupts Input pin for transition from stop mode to active mode Serial interface clock input/output pin Serial interface receive data input pin Serial interface transmit data output pin Timer output pin Event count input pin Square waveform output pin
28, 29 32 2 3 4 5 30 31
I I I/O I O O I O
Serial interface SCK SI SO Timer TOC EVNB Alarm BUZZ
4
HD404339 Series
Pin Number Item A/D converter Symbol AVCC DP-64S 32 FP-64B 26 I/O Function Power supply for the A/D converter. Connect this pin as close as possible to the VCC pin and at the same voltage as VCC. If the power supply voltage to be used for the A/D converter is not equal to V CC, connect a 0.1-F bypass capacitor between the AV CC and AV SS pins. (However, this is not necessary when the AV CC pin is directly connected to the VCC pin.) Ground for the A/D converter. Connect this pin as close as possible to GND at the same voltage as GND. I Analog input pins for the A/D converter
AVSS
19
13
AN 0-AN 11 20-31
14-25
5
HD404339 Series
Pin Description in PROM Mode
The HD4074339 is a PROM version of a ZTATTM microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM.
Pin Number DP-64S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 FP-64B 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MCU Mode Pin R6 0 R6 1 R6 2 R6 3 R7 0 R7 1 R7 2 R0 0/SCK R0 1/SI R0 2/SO R0 3/TOC TEST RESET OSC 1 OSC 2 GND X1 X2 AVSS R3 0/AN0 R3 1/AN1 R3 2/AN2 R3 3/AN3 R4 0/AN4 R4 1/AN5 R4 2/AN6 R4 3/AN7 R5 0/AN8 R5 1/AN9 R5 2/AN10 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O -- I O -- I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND O0 O1 O2 O3 O4 O5 O6 O7 I/O I/O I/O I/O I/O I/O I/O I/O GND GND VPP RESET VCC I VCC VCC PROM Mode Pin O4 O3 O2 O1 O0 I/O I/O I/O I/O I/O I/O
6
HD404339 Series
Pin Number DP-64S 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 FP-64B 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 MCU Mode Pin R5 3/AN11 AVCC VCC D0 /INT0 D1 /INT1 D2 /EVNB D3 /BUZZ D4 /STOPC D5 D6 D7 D8 D9 D10 D11 D12 D13 R8 0 R8 1 R8 2 R8 3 R9 0 R9 1 R9 2 R9 3 R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 RA 1/V disp I/O I/O -- -- I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I A5 A6 A7 A8 A0 A10 A11 A12 I I I I I I I I CE OE A13 A14 I I I I A3 A4 A9 VCC I I I VCC VCC M0 M1 A1 A2 I I I I PROM Mode Pin I/O
Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin 2. O0 to O 4 consist of two pins each. Tie each pair together before using them.
7
HD404339 Series
Block Diagram
STOPC RESET
OSC1
OSC2
TEST
GND
VCC
X1
X2
D0 INT0 Interrupt control INT1 System control RAM (512 x 4 bits) D port D1 D2 D3 D4 D5 D6 D7 D8 D9 X (4 bits) D10 D11 D12 D13 R0 port EVNB Timer B SPX (4 bits) Y (4 bits) TOC Timer C Internal data bus Internal address bus R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 R60 R61 R62 R63 R70 R71 R72 R80 R81 R82 R83 R90 R91 R92 R93 RA1
Timer A
W (4 bits)
SI SO SCK Serial interface
AV SS
AN 0
* * * AN11
A/D converter
ST (1 bit)
CA (1 bit)
B (4 bits) BUZZ Buzzer SP (10 bits) Data bus Instruction decoder PC (14 bits)
Directional signal line
8
RA port
ROM (16,384 x 10 bits) (6,144 x 10 bits) (12,288 x 10 bits) (4,096 x 10 bits) (8,192 x 10 bits)
R9 port
High voltage pin
R8 port
R7 port
R6 port
AVCC
A (4 bits)
R5 port
* * *
R4 port
ALU
R3 port
R2 port
SPY (4 bits)
Internal data bus
R1 port
HD404339 Series
Memory Map
ROM Memory Map Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$0FFF (HD404334), $0000-$17FF (HD404336), $0000-$1FFF (HD404338), $0000-$2FFF (HD4043312), $0000-$3FFF (HD404339, HD4074339)): The entire ROM area can be used for program coding.
$0000 $000F $0010 Zero-page subroutine (64 words) $003F $0040 $0FFF $1000 $17FF $1800 $1FFF $2000 HD4043312 Program (12,288 words) $2FFF $3000 HD404339, HD4074339 Program (16,384 words) $3FFF Pattern (4,096 words) HD404334 Program (4,096 words) HD404336 Program (6,144 words) HD404338 Program (8,192 words) Vector address (16 words)
$0000 JMPL instruction $0001 (jump to RESET, STOPC routine) JMPL instruction $0002 (jump to INT 0 routine) $0003 JMPL instruction $0004 (jump to INT 1 routine) $0005 JMPL instruction $0006 (jump to timer A routine) $0007 $0008 JMPL instruction (jump to timer B routine) $0009 $000A JMPL instruction (jump to timer C routine) $000B $000C JMPL instruction $000D (jump to A/D converter routine) $000E JMPL instruction (jump to serial routine) $000F
Note:
Since the ROM address areas between $0000-$0FFF overlap, the user can determine how these areas are to be used.
Figure 1 ROM Memory Map
9
HD404339 Series
RAM Memory Map
Initial values after reset $000 RAM-mapped registers $040 $050 Memory registers (MR) $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) W W R/W R/W W W R/W R/W W W R/W R/W 0000 0000
Undefined Undefined
Data (432 digits)
0000 0000
*2/0000 Undefined *1
$200
0000 0000 *2/0000
Undefined
Not used
Not used $3C0 Stack (64 digits) $3FF $016 $017 $018 $019 $01A A/D channel register A/D data register lower A/D data register upper A/D mode register 1 A/D mode register 2 (ACR) (ADRL) (ADRU) (AMR1) (AMR2) W R R W W 0000 0000 1000 0000 -000
Not used
$020 Register flag area $023 $024 Port mode register B (PMRB) $025 Port mode register C (PMRC) $026 Timer mode register B2 (TMB2) $027 System clock selection register 1 (SSR1) System clock selection register 2 (SSR2) $028
W W W W W
0000 00-0 -000 000--00
Not used Notes: 1. Two registers are mapped on the same area ($00A, $00B, $00E, $00F). $030 2. Undefined. Not used R: Read only W: Write only R/W: Read/write $033 $034 $035 $036 $037 Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Not used $03F $00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) W W W W W 0000 0000 0000 0000 -000 Port R0 DCR (DCR0) W 0000
Figure 2 RAM Memory Map and Initial Values
10
HD404339 Series
Table 1
Item Interrupt flags/mask Interrupt enable flag (IE) Interrupt request flag (IF) Interrupt mask (IM) Bit registers Watchdog timer on flag (WDON) A/D start flag (ADSF) Input capture status flag (ICSF) Input capture error flag (ICEF) I AD off flag (IAOF) RAM enable flag (RAME) Low speed on flag (LSON) Direct transfer on flag (DTON)
Initial Values of Flags after MCU Reset
Initial Value 0 0 1 0 0 0 0 0 0 0 0
RAM Address
$0000
Bit 3 IM0 (IM of INT0)
Bit 2
Bit 1
Bit 0
IE (Interrupt enable flag)
IF0 (IF of INT0)
RSP (Reset SP bit)
$0001
IMTA (IM of timer A)
IMTC (IM of timer C) IMS (IM of serial)
IFTA (IF of timer A) IFTC (IF of timer C)
IM1 (IM of INT1)
IMTB (IM of timer B) IMAD (IM of A/D)
IF1 (IF of INT1)
IFTB (IF of timer B)
IFAD (IF of A/D)
$0002
$0003
IFS (IF of serial)
Interrupt control bits area
Bit 3
$020 DTON (Direct transfer on flag)
Bit 2
ADSF (A/D start flag)
Bit 1
WDON (Watchdog on flag)
Bit 0
LSON (Low speed on flag)
$021
IF: Interrupt request flag $022 IM: Interrupt mask IE: Interrupt $023 enable flag SP: Stack pointer
RAME (RAM enable flag)
IAOF (IAD off flag)
ICEF (Input capture error flag)
ICSF (Input capture status flag)
Not used
Register flag area
Figure 3 Interrupt Control Bits and Register Flag Areas Configuration
11
HD404339 Series
SEM/SEMD IE IM LSON IAOF IF ICSF ICEF RAME RSP WDON ADSF DTON Not executed Allowed Allowed Allowed Not executed Inhibited Inhibited Inhibited Allowed Allowed Not executed Allowed Allowed Allowed REM/REMD Allowed TM/TMD Allowed
Not executed in active mode Allowed Used in subactive mode
Not used
Not executed
Not executed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instruction must not be executed for ADSF during A/D conversion. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
Memory registers $040 MR(0) $041 MR(1) $042 MR(2) $043 MR(3) $044 MR(4) $045 MR(5) $046 MR(6) $047 MR(7) $048 MR(8) $049 MR(9) $04A MR(10) $04B MR(11) $04C MR(12) $04D MR(13) $04E MR(14) $04F MR(15) Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 $3FF Level 1
$3C0
Bit 3 $3FC $3FD $3FE $3FF ST PC 10 CA PC 3
Bit 2 PC13 PC9 PC6 PC2
Bit 1 PC 12 PC 8 PC 5 PC 1
Bit 0 PC11 PC7 PC4 PC0
PC13 -PC0 : Program counter ST: Status flag CA: Carry flag
Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position
12
HD404339 Series
Registers and Flags
3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) 0 Carry Initial value: Undefined, R/W (CA) 0 Status Program counter Initial value: 0, no R/W Stack pointer Initial value: $3FF, no R/W Initial value: 1, no R/W 13 (PC) 9 1 1 1 1 5 (SP) 0 (ST) 0 (SPX) 0 (Y) 0 (X) 0 0 (W) 0 (A) 0 0
Figure 6 Registers and Flags
13
HD404339 Series
Addressing Modes
RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode (LAMR, XMRA): The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.
103
03
0
3
0
W
X
Y
Instruction
Opcode
9
7
3
0
9
0
RAM address Register Indirect Addressing
RAM address 0 0 0 1 0 0 Memory Register Addressing
9
1st instruction word Opcode
09
2nd instruction word
0
Instruction
9
0
RAM address Direct Addressing
Figure 7 RAM Addressing Modes
14
HD404339 Series
ROM Addressing Modes Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. Current Page Addressing Mode: A program can branch to any address in the current page (256 words per page) by executing the BR instruction. Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page subroutine area ($0000-$003F) by executing the CAL instruction. Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the B register by executing the TBR instruction.
1st instruction word
9 3 09
2nd instruction word
0
Opcode
9
5
0
Opcode
Operand
Operand
13
0
13
0
Program counter Direct Addressing
Program counter 0 0 0 0 0 0 0 0 Zero-Page Addressing
Operand Opcode
9 7 0 9 3 07 0
Operand
13 0
Opcode
13
B
A
0
Program counter * * * * * * Current Page Addressing
Program counter 0 0 Table Data Addressing
Figure 8 ROM Addressing Modes
15
HD404339 Series
Instruction Set
Table 2 Instruction Set Classification
Function Transferring constants to the accumulator, B register, and RAM. Number of Instructions 4
Instruction Type Immediate Register-to-register RAM addressing RAM register Arithmetic Compare RAM bit manipulation ROM addressing Input/output Control
Transferring contents of the B, Y, SPX, SPY, or memory registers to 8 the accumulator. Available when accessing RAM in register indirect addressing mode. Transferring data between the accumulator and memory. Performing arithmetic operations with the contents of the accumulator, B register, or memory. Comparing contents of the accumulator or memory with a constant. Bit set, bit reset, and bit test. Branching and jump instructions based on the status condition. Controlling the input/output of the R and D ports; ROM data reference with the P instruction. Controlling the serial communication interface and low-power dissipation modes. 13 10 25 12 6 8 11 4 Total: 101 instructions
16
HD404339 Series
Interrupts
$000,0 IE (RESET, STOPC) $000,2 INT0 interrupt IF0 $000,3 IM0 $001,0 INT1 interrupt IF1 $001,1 IM1 $001,2 Timer A interrupt IFTA $001,3 IMTA $002,0 Timer B interrupt IFTB $002,1 IMTB $002,2 Timer C interrupt IFTC $002,3 IMTC $003,0 A/D interrupt IFAD $003,1 IMAD $003,2 Serial interrupt IFS $003,3 IMS Priority Controller Priority Order Vector Address $0000 1 $0002 2 $0004 3 $0006 4 $0008 5 $000A 6 $000C 7 $000E Interrupt request
Figure 9 Interrupt Control Circuit
17
HD404339 Series
Instruction cycles 1 2 3 4 5 6
Instruction execution*
Stacking Interrupt acceptance IE reset Vector address generation
Execution of JMPL instruction at vector address
Execution of instruction at start address of interrupt routine
Note: * The stack is accessed and the interrupt enable flag is reset after the instruction is executed, even if it is a two-cycle instruction.
Figure 10 Interrupt Processing Sequence
18
HD404339 Series
Operating Modes
The MCU has five operating modes as shown in table 3. Transitions between operating modes are shown in figure 11. Table 3
Function System oscillator
Operations in Each Operating Mode
Active Mode OP Subactive Mode Stopped OP OP OP OP OP OP Stopped OP Standby Mode Watch Mode OP OP Retained Retained OP OP OP OP Retained Stopped OP Retained Retained OP Stopped Stopped Stopped Retained Stop Mode Stopped * OP Reset Retained Reset Reset Reset Reset Reset
Subsystem oscillator OP CPU RAM Timer A Timers B, C Serial A/D I/O OP OP OP OP OP OP OP
Notes: OP implies in operation. * Oscillation can be switched on or off with bit 3 of system clock selection register 1 (SSR1: $027).
19
HD404339 Series
Reset by RESET input or by watchdog timer
Stop mode
(TMA3 = 0, SSR13 = 0)
RAME = 0 RESET 1
RAME = 1 RESET 2
STOPC
STOPC
Active mode SBY instruction Interrupt STOP instruction STOP instruction
fOSC: fX: o CPU: o CLK: o PER:
Stop Oscillate Stop Stop Stop
Standby mode
(TMA3 = 0, SSR13 = 1)
fOSC: fX: o CPU: o CLK: o PER:
Oscillate Oscillate Stop fcyc fcyc
fOSC: fX: o CPU: o CLK: o PER:
Oscillate Oscillate fcyc fcyc fcyc
(TMA3 = 0)
fOSC: fX: o CPU: o CLK: o PER:
Stop Stop Stop Stop Stop
Watch mode fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate Stop fW fcyc SBY instruction Interrupt
(TMA3 = 1)
fOSC: fX: o CPU: o CLK: o PER:
Oscillate Oscillate fcyc fW fcyc
STOP instruction INT0, timer A *2
(TMA3 = 1, LSON = 0)
fOSC: fX: o CPU: o CLK: o PER:
Stop Oscillate Stop fW Stop
Main oscillation frequency Subsystem oscillation frequency for time base fcyc: fOSC/4, fOSC/8, fOSC/16, or fOSC/32 (software selectable) fSUB: fX/8 or fX/4 (software selectable) fW: fX/8 o CPU: System clock o CLK: Clock for timer A o PER: Clock for other peripheral functions (except timer A) LSON: Low speed on flag DTON: Direct transfer on flag
fOSC: fX:
*1 Subactive mode fOSC: fX: o CPU: o CLK: o PER: Stop Oscillate fSUB fW fSUB STOP instruction *3 INT0, timer A
(TMA3 = 1, LSON = 1)
fOSC: fX: o CPU: o CLK: o PER:
Stop Oscillate Stop fW Stop
Notes: 1. STOP/SBY (DTON = 1, LSON = 0) 2. STOP/SBY (DTON = 0, LSON = 0) 3. STOP/SBY (DTON = Don't care, LSON = 1)
Figure 11 MCU Status Transitions
20
, ,

HD404339 Series
In stop mode, the system oscillator is stopped. To ensure a proper oscillation stabilization period of at least tRC when clearing stop mode, execute the cancellation according to the timing chart in figure 12. In watch and subactive modes, a timer A or INT0 interrupt can be accepted during the interrupt frame period T (see figure 13). Note: In watch and subactive modes, an interrupt will not be properly detected if the INT0 high or low level period is shorter than the interrupt frame period T. Thus, when operating in watch and subactive modes, maintain the INT0 high or low level period longer than period T to ensure interrupt detection.
Stop mode Oscillator Internal clock RESET or STOPC tres STOP instruction execution tres tRC (stabilization period)
Figure 12 Timing of Stop Mode Cancellation
Active mode
Watch mode
Oscillation stabilization period
Active mode
Interrupt strobe
INT0
Interrupt request generation
(During the transition from watch mode to active mode only)
T
T
t RC
Tx
T + tRC TX 2T + tRC
T: Interrupt frame length t RC : Oscillation stabilization period
Figure 13 Interrupt Frame
21
HD404339 Series
The MCU automatically provides an oscillation stabilization period tRC when operation switches from watch mode to active mode. The interrupt frame period T and one of three values for t RC can be selected with the miscellaneous register (MIS: $00C), as listed in figure 14. Operation can switch directly from subactive mode to active mode, as illustrated in figure 15. In this case, the transition time TD obeys the following relationship.
t RC < TD < T + t RC
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3
MIS2
MIS1 0
MIS0 0
T*1
tRC*1
Oscillation Circuit Conditions External clock input
Buffer control. Refer to figure 24.
0.24414 ms 0.12207 ms 0.24414 ms*2
0 1 1
1 0 1
15.625 ms 125 ms Not used
7.8125 ms 62.5 ms
Ceramic oscillator Crystal oscillator --
Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used. 2. The value is applied only when direct transfer operation is used.
Figure 14 Miscellaneous Register
22
HD404339 Series
STOP/SBY instruction execution Subactive mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T Interrupt frame period T: t RC : Oscillation stabilization time t RC MCU internal processing period Oscillation stabilization time
Active mode
Figure 15 Direct Transition Timing MCU Operation Sequence: The MCU operation flow is shown in figures 16 and 17. RESET input is asynchronous, and causes an immediate transition to the reset state from any MPU operation state. The low-power mode operation sequence is shown in figure 17. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.
23
HD404339 Series
Power on
RESET = 0?
No
Yes
MCU operation cycle
RAME = 0
Yes MCU reset
IF = 1?
No No
IM = 0 IE = 1
Yes
Instruction RAME = 1 execution Reset input
Yes
SBY/STOP instruction
IE 0 Stack (PC), (CA), (ST)
No
Power-down mode operation cycle (see figure 17)
PC (PC)+1
PC vector address
Figure 16 MCU Operation Sequence (Power On)
24
HD404339 Series
Low-power mode operation cycle
IF = 1 and IM = 0?
No
Yes
Standby mode
Stop mode
No
IF = 1 and IM = 0?
No
STOPC = 0?
Yes Hardware NOP execution Hardware NOP execution
Yes
RAME = 1
PC Next Iocation
PC Next Iocation
Reset MCU
Instruction execution
MCU operation cycle
Figure 17 MCU Operating Sequence (Low-Power Mode Operation)
25
HD404339 Series
Oscillator Circuit
Figure 18 shows a block diagram of the clock generation circuit. The system clock frequency of the oscillator connected to OSC1 and OSC2 can be selected by system clock selection registers 1 and 2 (SSR1, 2: $027, $028) as shown in figures 20 and 21. The system clock division ratio can be set by software to be 1/4, 1/8, 1/16, or 1/32. The subsystem clock division ratio can be set by software to be 1/4 or 1/8.
LSON
OSC2 OSC1
System fOSC 1/4, 1/8, fcyc 1/16, or oscillator tcyc 1/32 division circuit *1
Timing generator circuit
o CPU System clock selection o PER
CPU with ROM, RAM, registers, flags, and I/O
Peripheral function interrupt
fX
X1 X2
Subsystem oscillator
fSUB 1/8 or 1/4 Timing division tsubcyc generator circuit *2 circuit TMA3
1/8 division circuit
fW tWcyc
Timing generator circuit
Time-base clock oCLK selection
Time-base interrupt
Notes: 1. The system clock division ratio can be selected by setting bit 1 or 0 of the system clock select register 2 (SSR2: $028). 2. The system clock division ratio can be selected by setting bit 2 of the system clock select register 1 (SSR1: $027).
Figure 18 Clock Generation Circuit
26
HD404339 Series
GND RESET
OSC1
OSC2
GND
X1
X2
AVSS
Figure 19 Typical Layout of Crystal and Ceramic Oscillators
27
HD404339 Series
Table 4 Oscillator Circuit Examples
Circuit Configuration External clock operation
External oscillator OSC 1
Circuit Constants
Open
OSC 2
Ceramic oscillator (OSC1, OSC 2)
C1 OSC1 Ceramic Rf OSC2 C2 GND
Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20%
Crystal oscillator (OSC1, OSC 2)
C1
Rf = 1 M 20%
OSC1
C1 = C2 = 10 to 22 pF 20% Crystal: Equivalent to circuit shown below C0 = 7 pF max.
Crystal
Rf OSC2
C2 GND L
OSC1
RS = 100 max.
CS
RS
OSC2
C0
Crystal oscillator (X1, X2)
C1 X1 Crystal X2 C2 GND L X1 C0 CS RS X2
Crystal: 32.768 kHz: MX38T (Nippon Denpa) C1 = C2 = 20 pF 20% RS = 14 k C0 = 1.5 pF
Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC 2, X1, X2 and elements should be as short as possible, and must not cross other wiring (see figure 19). 3. When a 32.768-kHz crystal oscillator is not used, fix pin X1 to GND and leave pin X2 open.
28
HD404339 Series
System clock selection register 1 (SSR1: $027) Bit Initial value Read/Write Bit name 3 0 W 2 0 W 1 0 W 0 -- --
SSR13*1 SSR12
SSR11 Not used SSR11 0 1 System Clock Selection*2 0.4 to 1.0 MHz 1.6 to 4.5 MHz 32-kHz Oscillation Division Ratio Selection fSUB = fX/8 fSUB = fX/4 32-kHz Oscillation Stop Oscillation operates in stop mode Oscillation stops in stop mode
SSR12 0 1 SSR13 0 1
Notes: *1 SSR13 will only be cleared to 0 by a RESET input. A STOPC input during stop mode will not clear SSR13. Also note that SSR13 will not be cleared upon transition to stop mode. *2 When the subsystem oscillator (32.768 kHz crystal oscillator) is used, set 0.4 MHz fOSC 1.0MHz or 1.6 MHz fOSC 4.5 MHz.
Figure 20 System Clock Selection Register 1 (SSR1)
System clock selection register 2 (SSR2: $028) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 W 0 0 W SSR20
Not used Not used SSR21
SSR21 0 0 1 1
SSR20 0 1 0 1
System Clock Division Ratio 1/4 division 1/8 division 1/16 division 1/32 division
Figure 21
System Clock Selection Register 2 (SSR2)
29
HD404339 Series
I/O Ports
The MCU has 53 input/output pins (D0-D13, R00-R9 3) and one input-only pin (RA1). * The 30 pins consisting of ports D0-D13, R1, R2, R8, and R9 are all high-voltage I/O pins. RA1 is a highvoltage input-only pin. The high-voltage pins can be equipped with or without pull-down resistance, as selected by the mask option. * All standard voltage output pins are CMOS output pins. However, the R0 2/SO pin can be programmed for NMOS open-drain output. * In stop mode, input/output pins go to the high-impedance state. * All standard voltage input/output pins have pull-up MOS built in, which can be individually turned on or off by software (Table 5). Pull-up MOS on/off settings can be made independently of settings as on-chip supporting module pins. Table 5 Control of Standard I/O Pins by Program
0 0 0 PMOS NMOS Pull-up MOS Note: -- indicates off. -- -- -- 1 -- -- -- 1 0 -- On -- 1 On -- -- 1 0 0 -- -- -- 1 -- -- On 1 0 -- On -- 1 On -- On
MIS3 (bit 3 of MIS) DCR PDR CMOS buffer
30
HD404339 Series
Data control register DCR0, DCR3 to DCR7 Bit Initial value Read/Write Bit name 3 0 W 2 0 W 1 0 W 0 0 W Bits 0 to 3 CMOS Buffer Control 0 1 CMOS buffer off (high impedance) CMOS buffer on (DCR0: $030, DCR3 to DCR7: $033 to $037)
DCR03, DCR02, DCR01, DCR00, DCR33 DCR32 DCR31 DCR30 to to to to DCR63 DCR72 DCR71 DCR70 Correspondence between ports and DCR bits Register DCR0 DCR3 DCR4 DCR5 DCR6 DCR7 Bit 3 R03 R33 R43 R53 R63 Not used Bit 2 R02 R32 R42 R52 R62 R72 Bit 1 R01 R31 R41 R51 R61 R71 Bit 0 R00 R30 R40 R50 R60 R70
Figure 22 Data Control Register (DCR)
31
HD404339 Series
Table 6
I/O Pin Type Input/output pins
Circuit Configurations of Standard I/O Pins
Circuit
VCC HLT VCC Pull-up control signal Buffer control signal Output data Input data Input control signal VCC HLT VCC Pull-up control signal Buffer control signal MIS3 DCR MIS2 PDR MIS3 DCR PDR
Pins R0 0, R0 1, R0 3, R3 0-R3 3, R4 0-R4 3, R5 0-R5 3, R6 0-R6 3, R7 0-R7 2 R0 2
Output data Input data Input control signal
Peripheral function Input/ pins output pins
VCC
HLT VCC Pull-up control signal MIS3
SCK
Output data Input data SCK
SCK
Output pins
VCC
HLT VCC Pull-up control signal MIS3
SO
PMOS control signal Output data
MIS2 SO HLT
VCC
TOC
VCC
Pull-up control signal
MIS3
Output data
TOC
32
HD404339 Series
I/O Pin Type Peripheral function Input/ pins pins Circuit
VCC HLT MIS3 PDR SI
Pins SI
Input data VCC
AN 0-AN 11
HLT MIS3 PDR A/D input
Input control
Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins enter the high-impedance state. 2. The HLT signal is 1 in active, standby, watch, and subactive modes.
Table 7
I/O Pin Type Input/output pins
Circuit Configurations for High-Voltage Input/Output Pins
With Pull-Down Resistance
VCC HLT Output data Pull-down resistance Vdisp Input data Input control signal Input control signal
Without Pull-Down Resistance
VCC HLT Output data Input data
Pins D0-D 13 , R1 0-R1 3, R2 0-R2 3, R8 0-R8 3, R9 0-R9 3
Input pins
Input control signal
Input data
RA 1
Peripheral function pins
Output pins
VCC
HLT Output data
VCC
BUZZ
HLT Output data
Pull-down resistance Vdisp
Input pins
Pull-down resistance Vdisp
Input data
Input data
INT0, INT1, EVNB, STOPC
Note: HLT goes high in active, standby, watch, and subactive modes.
33
HD404339 Series
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 0 W PMRA3 2 0 W 1 0 W 0 0 W
PMRA2 PMRA1 PMRA0 PMRA0 R02/SO Mode Selection R02 SO R01/SI Mode Selection R01 SI
PMRA2 0 1 PMRA3 0 1
R03/TOC Mode Selection R03 TOC D3/BUZZ Mode Selection D3 BUZZ
0 1 PMRA1 0 1
Figure 23 Port Mode Register A (PMRA)
Port mode register B (PMRB: $024) Bit Initial value Read/Write Bit name 3 0 W 2 0 W 1 0 W 0 0 W
PMRB3* PMRB2 PMRB1 PMRB0 PMRB0 D0/INT0 Mode Selection D0 INT0 D1/INT1 Mode Selection D1 INT1
PMRB2 D2/EVNB Mode Selection 0 1 D2 EVNB
0 1 PMRB1 0 1
PMRB3 D4/STOPC Mode Selection 0 1 D4 STOPC
Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not reset but retains its value.
Figure 24 Port Mode Register B (PMRB)
34
HD404339 Series
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3 0 1
Pull-Up MOS On/Off Selection Pull-up MOS off Pull-up MOS on (refer to table 5)
MIS2 0 1
CMOS Buffer On/Off Selection for Pin R02/SO CMOS on CMOS off
MIS1
MIS0
tRC selection. Refer to figure 14 in the operation modes section.
Note: The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
Figure 25 Miscellaneous Register
35
HD404339 Series
Prescaler
The MCU has two built-in prescalers, S and W (PSS, PSW). They divide the system clock and subsystem clock, and output these divided clocks to the peripheral function modules, as shown in figure 26.
Subsystem clock
fX/8
Prescaler W
Timer A Timer B Timer C
fX/4 or fX/8
System clock
Clock selector
Prescaler S
Serial
Figure 26 Prescaler Output Supply
36
HD404339 Series
Timers
The MCU has three built-in timers A, B, and C. The functions of each timer are listed in table 7. Timer A Timer A is an 8-bit free-running timer that can also be used as a clock time-base with a 32.768-kHz subsystem oscillator. Timer A has the following features: * One of eight internal clocks can be selected from prescaler S according to the setting of timer mode register A (TMA: $008) * In time-base mode, one of five internal clocks can be selected from prescaler W according to the setting of timer mode register A * An interrupt request can be generated when timer counter A (TCA) overflows * Input clock frequency must not be modified during timer A operation Table 7
Functions Clock source Prescaler S Prescaler W External event Timer functions Free-running Time base Event counter Reload Watchdog Input capture Timer output PWM
Timer Functions
Timer A Available Available -- Available Available -- -- -- -- -- Timer B Available -- Available Available -- Available Available -- Available -- Timer C Available -- -- Available -- -- Available Available -- Available
37
HD404339 Series
32.768-kHz oscillator 1/4 1/2 2 fW 1/2 t Wcyc Selector Internal data bus Selector Clock Timer counter A (TCA) Overflow fW t Wcyc Prescaler W (PSW)
/2 /8 / 16 / 32
Timer A interrupt request flag (IFTA)
Selector
/2 /4 /8 / 32 / 128 / 512 / 1024 / 2048
System clock
oPER
Prescaler S (PSS)
3 Timer mode register A (TMA)
Figure 27 Timer A Block Diagram
38
HD404339 Series
Timer mode register A (TMA: $008) Bit Initial value Read/Write Bit name 3 0 W TMA3 2 0 W TMA2 1 0 W TMA1 0 0 W TMA0
Source Input Clock TMA3 TMA2 TMA1 TMA0 Prescaler Frequency Operating Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 X = Don't care. Notes: 1. t Wcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. X PSS PSS PSS PSS PSS PSS PSS PSS PSW PSW PSW PSW PSW Not used PSW and TCA reset 2048 tcyc 1024 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc 4 tcyc 2 tcyc 32t Wcyc 16t Wcyc 8t Wcyc 2t Wcyc 1/2t Wcyc Time-base mode Timer A mode
Figure 28 Timer Mode Register A (TMA)
39
HD404339 Series
Timer B Timer B is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features. These are described as follows. * By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler S can be selected, or timer B can be used as an external event counter * By setting timer mode register B2 (TMB2: $026), detection edge type of EVNB can be selected. * By setting timer write register BL, U (TWBL, U: $00A, $00B), timer counter B (TCB) can be written to during reload timer operation * By setting timer read register BL, U (TRBL, U: $00A, $00B), the contents of timer counter B can be read out * Timer B can be used as an input capture timer to count the clock cycles between trigger edges input as an external event * An interrupt can be requested when timer counter B overflows or when a trigger input edge is received during input capture operation
40
HD404339 Series
Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU)
Timer read register B lower (TRBL)
Clock Internal data bus 41 Free-running timer control signal Timer counter B (TCB) Overflow
Timer write register B upper (TWBU) Timer write register B lower (TWBL)
EVNB Edge detector oPER
Selector /2 /4 /8 / 32 / 128 / 512 / 2048
3 Timer mode register B1 (TMB1)
System clock
Prescaler S (PSS) Edge detection control signal
2
Timer mode register B2 (TMB2)
Figure 29 Timer B Free-Running and Reload Operation Block Diagram
HD404339 Series
Input capture status flag (ICSF) Error controller Input capture error flag (ICEF) Interrupt request flag of timer B (IFTB)
Timer read register BU (TRBU) Timer read register B lower (TRBL) EVNB Edge detector Read signal Clock Overflow Internal data bus Timer counter B (TCB) Input capture timer control signal
Selector /2 /4 /8 / 32 / 128 / 512 / 2048
3 Timer mode register B1 (TMB1)
System clock
oPER
Prescaler S (PSS)
2
Edge detection control signal Timer mode register B2 (TMB2)
Figure 30 Timer B Input Capture Operation Block Diagram
42
HD404339 Series
Timer mode register B1 (TMB1: $009) Bit Initial value Read/Write Bit name 3 0 W TMB13 2 0 W TMB12 1 0 W TMB11 0 0 W TMB10
TMB13 0 1
Free-Running/Reload Timer Selection Free-running timer Reload timer
TMB12 0
TMB11 0
TMB10 0 1
Input Clock Period and Input Clock Source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc D2/EVNB (External event input)
1
0 1
1
0
0 1
1
0 1
Figure 31 Timer Mode Register B1 (TMB1)
Timer mode register B2 (TMB2: $026) Bit Initial value Read/Write Bit name 3 -- -- 2 0 W 1 0 W TMB21 TMB21 0 0 0 W TMB20 TMB20 0 1 1 0 1 TMB22 0 1 EVNB Edge Detection Selection No detection Falling edge detection Rising edge detection Rising and falling edge detection
Not used TMB22
Free-Running/Reload and Input Capture Selection Free-Running/Reload Input Capture
Figure 32 Timer Mode Register B2 (TMB2)
43
HD404339 Series
Timer C Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are described as follows. * By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S can be selected * By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output (PWM output) is enabled * By setting timer write register CL, U (TWCL, U: $00E, $00F), timer counter C (TCC) can be written to * By setting timer read register CL, U (TRCL, U: $00E, $00F), the contents of timer counter C can be read out * An interrupt can be requested when timer counter C overflows * Timer counter C can be used as a watchdog timer for detecting runaway programs
44
HD404339 Series
System reset signal Watchdog on flag (WDON) Watchdog timer controller Interrupt request flag of timer C (IFTC)
Timer read register CU (TRCU) TOC Timer output control logic Timer read register C lower (TRCL)
Clock
Timer counter C (TCC) Timer output control signal
Overflow Internal data bus
Timer write register C upper (TWCU) Timer write register C lower (TWCL)
Selector /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048
Free-running timer control signal 3
System oPER clock
Prescaler S (PSS)
Timer mode register C (TMC)
Port mode register A (PMRA)
Figure 33 Timer C Block Diagram
45
HD404339 Series
Timer mode register C (TMC: $00D) Bit Initial value Read/Write Bit name 3 0 W TMC3 2 0 W TMC2 1 0 W TMC1 0 0 W TMC0
TMC3 0 1
Free-Running/Reload Timer Selection Free-running timer Reload timer
TMC2 0
TMC1 0
TMC0 0 1
Input Clock Period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc
1
0 1
1
0
0 1
1
0 1
Figure 34 Timer Mode Register C (TMC)
$FF + 1 Overflow Timer C count value
$00
Time
CPU operation
Normal operation
Timer C clear
Normal operation
Timer C clear
Program runaway
Reset
Normal operation
Figure 35 Watchdog Timer Operation Flowchart
46
HD404339 Series
T x (N + 1) TMC3 = 0 (Free-running timer) T TMC3 = 1 (Reload timer) T x (256 - N) Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are determined by timer mode register C.) N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.) T x 256
Figure 36 PWM Output Waveform
47
HD404339 Series
Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 8. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 8 PWM Output Following Update of Timer Write Register
PWM Output Mode Free running Timer Write Register is Updated during High PWM Output
Timer write register updated to value N
Timer Write Register is Updated during Low PWM Output
Timer write register updated to value N
Interrupt request
Interrupt request
T x (255 - N) T x (N + 1)
T x (N' + 1) T x (255 - N) T x (N + 1)
Reload
Timer write register updated to value N
Interrupt request
Timer write register updated to value N
Interrupt request
T
T x (255 - N)
T
T T x (255 - N) T
48
HD404339 Series
Alarm Output Function
The MCU has an alarm output function built in. By setting port mode register C (PMRC: $025), one of four alarm frequencies supplied from the PSS can be selected.
BUZZ Alarm output controller
Alarm output control signal
Selector /1024 /2048
2 Port mode register C (PMRC)
/256
System oPER clock
Prescaler S (PSS)
Figure 37 Alarm Output Function Block Diagram Table 9
PMRC Bit 3 0 Bit 2 0 1 1 0 1 System Clock Divisor / 2048 / 1024 / 512 / 256
Port Mode Register C
/512
Internal data bus 49
Port mode register A (PMRA)
HD404339 Series
Serial Interface
The MCU has a one-channel serial interface built in with the following features. * One of 13 different internal clocks or an external clock can be selected as the transmit clock. The internal clocks include the six prescaler outputs divided by two and by four, and the system clock. * During idle status, the serial output pin can be controlled to be high or low output * Transmit clock errors can be detected * An interrupt request can be generated after transfer has completed when an error occurs
SO Idle controller SCK I/O controller SI Clock
Octal counter (OC)
Serial interrupt request flag (IFS)
Serial data register (SR) Internal data bus
Selector 3 /2 /8 / 32 / 128 / 512 / 2048 Serial mode register (SMR)
System clock
oPER
Prescaler S (PSS)
Selector
1/2
1/2
Transfer control signal
Port mode register C (PMRC)
Figure 38 Serial Interface Block Diagram
50
HD404339 Series
Table 10
SMR Bit 3 1
Serial Interface Operating Modes
PMRA Bit 1 0 Bit 0 0 1 1 0 1 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode
STS wait state (Octal counter = 000, transmit clock disabled)
MCU reset
SMR write STS instruction Transmit clock Transmit clock wait state (Octal counter = 000)
SMR write (IFS 1)
Transfer state (Octal counter = 000)
8 transmit clocks or STS instruction (IFS 1)
External clock mode
SMR write
STS wait state (Octal counter = 000, transmit clock disabled)
MCU reset
Continuous clock output state (PMRA 0, 1 = 00)
SMR write STS instruction
8 transmit clocks or SMR write (IFS 1)
Transmit clock
Transmit clock
Transmit clock wait state (Octal counter = 000)
STS instruction (IFS 1)
Transfer state (Octal counter = 000)
Internal clock mode
Figure 39 Serial Interface State Transitions
51
HD404339 Series
Transmit clock 1 Serial output data Serial input data latch timing LSB 2 3 4 5 6 7 8 MSB
Figure 40 Serial Interface Timing
52
,
Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SMR write External clock selection Output level control in idle states PMRC write SRL, SRU write STS instruction Data write for transmission SCK pin (input) SO pin Undefined LSB IFS External clock mode Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SMR write Internal clock selection Output level control in idle states PMRC write SRL, SRU write STS instruction SCK pin (output) SO pin Data write for transmission Undefined LSB IFS Internal clock mode
HD404339 Series
Transmit clock wait state STS wait state
Dummy write for state transition Output level control in idle states
MSB
Flag reset at transfer completion
STS wait state
Output level control in idle states
MSB
Flag reset at transfer completion
Figure 41 Example of Serial Interface Operation Sequence
53
HD404339 Series
Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMR write IFS = 1 Yes No Normal termination Transmit clock wait state State SCK pin (input) Noise 1 2 3 4 SMR write IFS
Transmit clock errors are detected as illustrated in figure 42.
Transmit clock error processing
Transmit clock error detection flowchart Transmit clock wait state Transfer state
Transfer state
5
6
7 8 Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set.
Flag set because octal counter reaches 000. Transmit clock error detection procedure
Flag reset at transfer completion.
Figure 42 Transmit Clock Error Detection
54
HD404339 Series
Table 11
PMRC Bit 0 0
Transmit Clock Selection
SMR Bit 2 0 Bit 1 0 Bit 0 0 1 1 0 1 1 0 0 1 System Clock Divisor / 2048 / 512 / 128 / 32 /8 /2 / 4096 / 1024 / 256 / 64 / 16 /4 Transmit Clock Frequency 4096t cyc 1024t cyc 256t cyc 64t cyc 16t cyc 4t cyc 8192t cyc 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc
1
0
0
0 1
1
0 1
1
0
0 1
Serial mode register (SMR: $005) Bit Initial value Read/Write Bit name 3 0 W SMR3 2 0 W SMR2 1 0 W SMR1 0 0 W SMR0
SMR3 0 1
R00/SCK Mode Selection R00 SCK
SMR2 0
SMR1 0
SMR0 0 1
SCK Output
Clock Source Prescaler
Prescaler Division Ratio Refer to table 11
1
0 1
1
0
0 1
1
0 1
Output Input
System clock External clock
-- --
Figure 43 Serial Mode Register (SMR)
55
HD404339 Series
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 0 W PMRC3 2 0 W PMRC2 1
Undefined
0 0 W PMRC0
W PMRC1
PMRC0 Alarm output function. Refer to table 9. 0 1 PMRC1 0 1
Serial Clock Division Ratio Prescaler output divided by 2 Prescaler output divided by 4 Output Level Control in Idle States Low level High level
Figure 44 Port Mode Register C (PMRC)
56
HD404339 Series
A/D Converter
The MCU also contains a built-in A/D converter that uses a sequential comparison method with a resistance ladder. It can perform digital conversion of twelve analog inputs with 8-bit resolution. The following describes the A/D converter. * A/D mode register 1 (AMR1: $019) is used to select digital or analog ports * A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed and to select digital or analog ports * The A/D channel register (ACR: $016) is used to select an analog input channel * A/D conversion is started by setting the A/D start flag (ADSF: $020, 2) to 1. After the conversion is completed, converted data is stored in the A/D data register, and at the same time the A/D start flag is cleared to 0. * By setting the IAD off flag (IAOF: $021, 2) to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode * The A/D data register is a read-only register consisting of a lower 4 bits and upper 4 bits (ADRL: $017, ADRU: $018). This register is not cleared by a reset. Data reads during A/D conversion are not guaranteed. After A/D conversion ends, the resultant 8-bit data is set in this register and held until the start of the next conversion (figures 51 to 53).
57
HD404339 Series
4 A/D interrupt request flag (IFAD) 2 4 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 A/D mode register 2 (AMR2) A/D data register (ADRU, L) Internal data bus A/D mode register 1 (AMR1)
Selector + Comp -
Encoder
A/D controller
Control signal for conversion time
A/D channel register (ACR)
AVCC
A/D start flag (ADSF) D/A
IAD off flag (IAOF)
AVSS
Operating mode signal (1 in stop, watch, and subactive modes)
Figure 45 A/D Converter Block Diagram
58
HD404339 Series
Notes on Usage * Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF) * Do not write to the A/D start flag during A/D conversion * Data in the A/D data register during A/D conversion is undefined * Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D converter does not operate in stop, watch, or subactive mode. In addition, to save power while in these modes, all current flowing through the converter's resistance ladder is cut off. * If the power supply for the A/D converter is to be different from VCC, connect a 0.1-F bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) * The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode registr as an analog pin will remain pulled up.
A/D mode register 1 (AMR1: $019) Bit Initial value Read/Write Bit name 3 0 W AMR13 2 0 W AMR12 1 0 W AMR11 0 0 W AMR10 AMR10 AMR12 0 1 AMR13 0 1 R32/AN2 Mode Selection R32 AN2 R33/AN3 Mode Selection R33 AN3 0 1 AMR11 0 1 R30/AN0 Mode Selection R30 AN0 R31/AN1 Mode Selection R31 AN1
Figure 46 A/D Mode Register 1 (AMR1)
59
HD404339 Series
A/D mode register 2 (AMR2: $01A) Bit Initial value Read/Write Bit name 3 -- -- 2 0 W 1 0 W AMR21 0 0 W AMR20
Not used AMR22
AMR20 0 1 AMR22 0 1 R5/AN8-AN11 Pin Selection R5 AN8-AN11 AMR21 0 1
Conversion Time 34tcyc 67tcyc R4/AN4-AN7 Pin Selection R4 AN4-AN7
Figure 47 A/D Mode Register 2 (AMR2)
60
HD404339 Series
A/D channel register (ACR: $016) Bit Initial value Read/Write Bit name 3 0 W ACR3 2 0 W ACR2 1 0 W ACR1 0 0 W ACR0
ACR3 ACR2 ACR1 ACR0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Don't Don't care care
Analog Input Selection AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Not used
Figure 48 A/D Channel Register (ACR)
61
HD404339 Series
A/D start flag (ADSF: $020, bit 2) Bit Initial value Read/Write Bit name 3 0 R/W DTON 2 0 R/W ADSF 1 0 W WDON 0 0 R/W LSON
A/D Start Flag (ADSF) 0 1 A/D conversion completed A/D conversion started DTON Refer to the description of operating modes
LSON Refer to the description of operating modes
WDON Refer to the description of timers
Figure 49 A/D Start Flag (ADSF)
IAD off flag (IAOF: $021, bit 2) Bit Initial value Read/Write Bit name 3 0 R/W RAME 2 0 R/W IAOF 1 0 R/W ICEF 0 0 R/W ICSF
IAD Off Flag (IAOF) 0 1 IAD current flows IAD current is cut off
ICSF Refer to the description of timers
ICEF RAME Refer to the description of timers Refer to the description of operating modes
Figure 50 IAD Off Flag (IAOF)
62
HD404339 Series
ADRU: $018 3 2 1 0 3 ADRL: $017 2 1 0
MSB bit 7
LSB bit 0
RESULT
Figure 51 A/D Data Register
A/D data register (lower) (ADRL: $017) Bit Read/write Initial value after reset Bit name 3 R 0 ADRL3 2 R 0 ADRL2 1 R 0 ADRL1 0 R 0 ADRL0
Figure 52 A/D Data Register (Lower) (ADRL)
A/D data register (upper) (ADRU: $018) Bit Read/write Initial value after reset Bit name 3 R 1 ADRU3 2 R 0 ADRU2 1 R 0 ADRU1 0 R 0 ADRU0
Figure 53 A/D Data Register (Upper) (ADRU)
63
HD404339 Series
Notes on Mounting
Assemble all parts including the HD404339 Series on a board, noting the points described below. 1. Connect layered ceramic type capacitors (about 0.1 F) between AVCC and AVSS , between VCC and GND, and between used analog pins and AVSS . 2. Connect unused analog pins to AVSS .
64
HD404339 Series
1. When not using an A/D converter.
VCC
AVCC AN 0 0.1 F AN 1 to AN 11
GND
AVSS
2. When using pins AN 0 and AN 1 but not using AN 2 to AN 11. AVCC AN 0 AN 1 AN 2 to AN 11 GND 0.1 F x 3 AVSS
VCC
3. When using all analog pins. AVCC AN 0 AN 1 AN 2 to AN 11 AVSS 0.1 F x 13
VCC
GND
Figure 54 Example of Connections (AVCC to AVSS ) Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits. An example connection is described in figure 54. No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. The capacitors are a large capacitance C1 and a small capacitance C2.
65
HD404339 Series
VCC C1 C2 VCC
GND
GND
Figure 55 Example of Connections (VCC to GND)
66
HD404339 Series
Absolute Maximum Ratings
Item Supply voltage Programming voltage Pin voltage Symbol VCC VPP VT IO -IO IO Value -0.3 to +7.0 -0.3 to +14.0 -0.3 to VCC + 0.3 VCC - 45 to VCC + 0.3 Total permissible input current Total permissible output current Maximum input current 70 150 4 20 Maximum output current -I O 4 30 Operating temperature Storage temperature Topr Tstg -20 to +75 -55 to +125 Unit V V V V mA mA mA mA mA mA C C 1 2 3 4 5 6, 7 6, 8 9, 10 10, 11 Notes
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP ) of HD4074339. 2. Applies to all standard voltage pins. 3. Applies to high-voltage pins. 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to ports R3, R4, and R5. 8. Applies to ports R0, R6, and R7. 9. Applies to ports R0 and R3 to R7. 10. The maximum output current is the maximum current flowing from V CC to each I/O pin. 11. Applies to ports D0-D 13 , R1, R2, R8, and R9.
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HD404339 Series
Electrical Characteristics
DC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VC C, T a = -20 to +75C, unless otherwise specified)
Item Symbol Pins RESET, SCK, SI, INT0, INT1, STOPC, EVNB OSC 1 Input low voltage VIL RESET, SCK, SI VCC - 0.5 -- -0.3 -- VCC + 0.3 0.2V CC 0.2V CC 0.5 -- 0.4 1 V V V V V V A -I OH = 0.5 mA I OL = 0.4 mA Vin = 0 V to VCC 1 Min 0.8V CC Typ -- Max VCC + 0.3 Unit Test Condition V Notes
Input high voltage VIH
INT0, INT1, VCC - 40 -- STOPC, EVNB OSC 1 Output high voltage VOH -0.3 -- SCK, SO, TOC VCC - 0.5 -- SCK, SO, TOC -- RESET, SCK, SI, SO,TOC, OSC 1 -- -- --
Output low voltage VOL I/O leakage current |IIL|
INT0, INT1, -- STOPC, EVNB Current dissipation I CC in active mode VCC --
-- --
20 5.0
A mA
Vin = VCC - 40 to VCC VCC = 5 V, f OSC = 4 MHz
1 2, 5
-- Current dissipation I SBY in standby mode Current dissipation I SUB in subactive mode VCC VCC --
-- --
8.0 2.0
mA mA A A A A A V VCC = 5 V, 32 kHz oscillator X1 = GND, X2 = Open VCC = 5 V, f OSC = 4 MHz VCC = 5 V, 32 kHz oscillator
2, 6 3
--
--
100
4, 5
-- Current dissipation I WTC in watch mode Current dissipation I STOP in stop mode VCC VCC --
-- --
320 20
4, 6 4
--
--
10
4, 5
-- Stop mode retaining voltage VSTOP VCC 2
-- --
20 --
4, 6
68
HD404339 Series
Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. I CC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST at GND R0, R30 to R72 at V CC D0-D 13 , R1, R2, R8, R9, RA 1 at V disp 3. I SBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Standby mode Pins: RESET at V CC TEST at GND R0, R30 to R72 at V CC D0-D 13 , R1, R2, R8, R9, RA 1 at V disp 4. This is the source current when no I/O current is flowing. Test conditions: Pins: R0, R30 to R72 at V CC D0-D 13 , R1, R2, R8, R9, RA 1 at GND 5. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339. 6. Applies to the HD4074339.
69
HD404339 Series
I/O Characteristics for High-Voltage Pins (V CC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC - 40 V to VCC, T a = -20 to +75C, unless otherwise specified)
Item Symbol Pins D0-D 13 , R1, R2, R8, R9, RA 1 Input low voltage VIL D0-D 13 , R1, R2, R8, R9, RA 1 Output high voltage VOH D0-D 13 , R1, R2, R8, R9, BUZZ VCC - 2.0 -- VCC - 1.0 -- Output low voltage VOL D0-D 13 , R1, R2, R8, R9, BUZZ -- I/O leakage current |IIL| D0-D 13 , R1, R2, R8, R9, RA 1, BUZZ Pull-down MOS current I PD D0-D 13 , R1, R2, R8, R9 200 600 1000 A Vdisp = VCC - 35 V, Vin = VCC 1 -- -- -- VCC - 37 V 20 A 150 k at V CC - 40 V Vin = VCC - 40 V to VCC 2 3 -- -- -- -- V V -I OH = 10 mA -I OH = 4 mA Vdisp = VCC - 40 V 1 VCC - 3.0 -- -- V -I OH = 15 mA VCC - 40 -- 0.3V CC V Min 0.7V CC Typ Max -- Unit Test Condition Note
Input high voltage VIH
VCC + 0.3 V
VCC - 37 V
Notes: 1. Applies to pins with pull-down MOS as selected by the mask option . 2. Applies to pins without pull-down MOS as selected by the mask option. 3. Excludes output buffer current.
70
HD404339 Series
A/D Converter Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC - 40 V to VCC, Ta = -20 to +75C, unless otherwise specified)
Item Analog supply voltage Analog input voltage Symbol AVCC AVin Pins AVCC AN 0-AN 11 Min Typ Max VCC + 0.3 AVCC 200 Unit V V A VCC = AVCC = 5.0 V Test Condition Note 1
VCC - 0.3 VCC AVSS -- -- --
Current flowing I AD between AV CC and AVSS Analog input capacitance Resolution Number of input channels Absolute accuracy Conversion time Input impedance AN 0-AN 11 CA in AN 0-AN 11
-- 8 0 -- 34 1
-- 8 -- -- -- --
30 8 12 2.0 67 --
pF Bit Channel LSB t cyc M
Note: 1. Connect this to V CC if the A/D converter is not used.
71
HD404339 Series
AC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC - 40 V to VCC, T a = -20 to +75C)
Item Clock oscillation frequency Symbol Pins f OSC OSC 1, OSC 2 X1, X2 Instruction cycle time t cyc t subcyc Min 0.4 Typ 4 Max 4.5 Unit MHz Test Condition System clock divided by 4 -- 0.89 -- 32.768 -- 1 10 kHz s s 32-kHz oscillator, 1/8 system clock division ratio -- 122.07 -- s 32-kHz oscillator, 1/4 system clock division ratio Oscillation stabilization time t RC (ceramic oscillator) Oscillation stabilization time t RC (crystal oscillator) OSC 1, OSC 2 OSC 1, OSC 2 X1, X2 External clock high width External clock low width External clock rise time External clock fall time INT0, INT1, EVNB high widths t CPH t CPL t CPr t CPf t IH OSC 1 OSC 1 OSC 1 OSC 1 INT0, INT1, EVNB INT0, INT1, EVNB RESET low width STOPC low width RESET rise time STOPC rise time Input capacitance t RSTL t STPL t RSTr t STPr Cin RESET STOPC RESET STOPC 2 1 -- -- -- -- -- -- -- -- -- 20 20 30 2 -- -- -- -- -- 92 92 -- -- 2 -- -- -- -- -- -- -- -- 7.5 40 2 -- -- 20 20 -- ms ms s ns ns ns ns t cyc / t subcyc t cyc / t subcyc t cyc t RC ms ms pF f = 1 MHz, Vin = 0 V -- 30 pF f = 1 MHz, Vin = 0 V -- -- 180 pF 8 Notes: 1. When using the subsystem oscillator (32.768 kHz), one of the following relationships for f OSC must be applied. 0.4 MHz fOSC 1.0 MHz or 1.6 MHz fOSC 4.5 MHz The operating range for fOSC can be set with bit 1 of system selection register 1 (SSR1: $027). 2. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: 7 5 6 5 6 4 2 2 2 3 3 3 3 4 1 Note 1
244.14 --
INT0, INT1, EVNB low widths t IL
All input -- pins except TEST TEST --
72
HD404339 Series
a. After V CC reaches 4.0 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of t RC. When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. Refer to figure 56. Refer to figure 57. Refer to figure 58. Refer to figure 59. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339. Applies to the HD4074339.
3. 4. 5. 6. 7. 8.
Serial Interface Timing Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC - 40 V to VCC, T a = -20 to +75C, unless otherwise specified) During Transmit Clock Output
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Transmit clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Symbol Pins t Scyc t SCKH t SCKL t SCKr t SCKf t DSO t SSI t HSI SCK SCK SCK SCK SCK SO SI SI Min 1 0.4 0.4 -- -- -- 100 200 Typ Max Unit Test Condition -- -- -- -- -- -- -- -- -- -- -- 80 80 300 -- -- t cyc t Scyc t Scyc ns ns ns ns ns Load shown in figure 61 Load shown in figure 61 Load shown in figure 61 Load shown in figure 61 Load shown in figure 61 Load shown in figure 61 Note 1 1 1 1 1 1 1 1
During Transmit Clock Input
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Transmit clock fall time Symbol t Scyc t SCKH t SCKL t SCKr t SCKf Pins SCK SCK SCK SCK SCK SO SI SI Min 1 0.4 0.4 -- -- -- 100 200 Typ Max Unit Test Condition -- -- -- -- -- -- -- -- -- -- -- 80 80 t cyc t Scyc t Scyc ns ns Load shown in figure 61 Note 1 1 1 1 1 1 1 1
Serial output data delay time t DSO Serial input data setup time Serial input data hold time Note: 1. Refer to figure 60. t SSI t HSI
300 ns -- -- ns ns
73
HD404339 Series
OSC1 1/fCP VCC - 0.5 V 0.5 V tCPr tCPH tCPL tCPf
Figure 56 External Clock Timing
INT0, INT1, EVNB
0.8VCC 0.2VCC
tIH
tIL
Figure 57 Interrupt Timing
RESET 0.8VCC tRSTL 0.2VCC tRSTr
Figure 58 RESET Timing
STOPC 0.8VCC tSTPL 0.2VCC tSTPr
Figure 59 STOPC Timing
74
HD404339 Series
t Scyc t SCKf SCK VCC - 2.0 V (0.8VCC )* 0.8 V (0.2VCC)* t DSO SO VCC - 2.0 V 0.8 V t SSI SI 0.8V CC 0.2VCC t HSI t SCKL t SCKH t SCKr
Note: * VCC - 2.0 V and 0.8 V are the threshold voltages for transmit clock output, and 0.8VCC and 0.2VCC are the threshold voltages for transmit clock input.
Figure 60 Serial Interface Timing
VCC RL = 2.6 k Test point C= 30 pF R= 12 k Hitachi 1S2074 or equivalent
Figure 61 Timing Load Circuit
75
HD404339 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404334 and HD404336 as an 8-kword version (HD404338), and to create the same data size for the HD4043312 as a 16-kword version (HD404339). The 8-kword and 16-kword data sizes are required to change ROM data to mask manufacturing data since the program used is for an 8-k or 16-kword version. This limitation applies when using an EPROM or a data base.
ROM 4-kword version: HD404334 Address $1000-$1FFF ROM 6-kword version: HD404336 Address $1800-$1FFF ROM 12-kword version: HD4043312 Address $3000-$3FFF
$0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (4,096 words) $0FFF $1000 Not used $1FFF
$0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (6,144 words) $17FF $1800 Not used $1FFF
$0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (12,288 words) $2FFF $3000 Not used $3FFF
Fill this area with 1s
76
HD404339 Series
HD404334/HD404336/HD404338/HD4043312/HD404339 Option List
Please check off the appropriate applications and enter the necessary information. 1. ROM Size HD404334 HD404336 HD404338 HD4043312 HD404339 2. Optional Functions * * With 32-kHz CPU operation, with time base for clock Without 32-kHz CPU operation, with time base for clock Without 32-kHz CPU operation, without time base Note: *Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. I/O Options D: Without pull-down resistance Pin name D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC D5 D6 D7 D8 D9 D10 D11 D12 D13 4. RA1/Vdisp RA1 without pull-down resistance Vdisp Note: If even only one pin is selected with I/O option E, pin RA1/Vdisp must be selected to function as Vdisp. 5. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 6. System Oscillator (OSC1, OSC2) Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz 7. Stop Mode Used Not used 8. Package FP-64B DP-64S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O D E: With pull-down resistance E Pin name R1 R10 R11 R12 R13 R20 R21 R22 R23 R80 R81 R82 R83 R90 R91 R92 R93 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O option D E 4-kword 6-kword 8-kword 12-kword 16-kword Date of order Customer Department Name ROM code name LSI number
I/O option
R2
R8
R9
77
HD404339 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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